It's more the economics of what sells that lets the power hungry monsters thrive. If you can tape out one chip design, and one gives you 1 TOPS and the other is 5 TOPS, the sales will go to the 5 TOPS because power is a downstream cost. That being said, it's only a matter of time before both chips are maximum TOPS and the only differentiator is power. My latest simulations are showing a competitive design around 70W, but I'm still confirming it and it would really be beneficial to do some data gathering tapeouts at larger nodes to feel like it's worth the risk of more expensive nodes.
Yes smaller nodes give lower power operation with faster transistor switching speeds. You can also underpower a node to intentionally cause slower transistor switching speeds.
Comments
It's more the economics of what sells that lets the power hungry monsters thrive. If you can tape out one chip design, and one gives you 1 TOPS and the other is 5 TOPS, the sales will go to the 5 TOPS because power is a downstream cost. That being said, it's only a matter of time before both chips are maximum TOPS and the only differentiator is power. My latest simulations are showing a competitive design around 70W, but I'm still confirming it and it would really be beneficial to do some data gathering tapeouts at larger nodes to feel like it's worth the risk of more expensive nodes.
Systolic hardware?
Race logic with pulses, it's a descent of systolic arrays. There is less of an array shape and more about time.
Dumb question, wouldn't node size impact the logic latency itself on some level?
Yes smaller nodes give lower power operation with faster transistor switching speeds. You can also underpower a node to intentionally cause slower transistor switching speeds.
Where can I find the whitepaper?