Comment on AI Chip ArchitecturesparentComments−skyberrys19dRace logic with pulses, it's a descent of systolic arrays. There is less of an array shape and more about time.−whaleofatw202219dDumb question, wouldn't node size impact the logic latency itself on some level?−skyberrys19dYes smaller nodes give lower power operation with faster transistor switching speeds. You can also underpower a node to intentionally cause slower transistor switching speeds.−brcmthrowaway19dWhere can I find the whitepaper?
Comments
Race logic with pulses, it's a descent of systolic arrays. There is less of an array shape and more about time.
Dumb question, wouldn't node size impact the logic latency itself on some level?
Yes smaller nodes give lower power operation with faster transistor switching speeds. You can also underpower a node to intentionally cause slower transistor switching speeds.
Where can I find the whitepaper?