The obvious answer: flash can hold multiple bits per cell and ram can't.
MLC is half as expensive as SLC. TLC is 33% less expensive than MLC. QLC is 25% less expensive than TLC and 75% cheaper than SLC. Not to mention transparent compression algos. As the controllers improve you can get more bits of storage from the same amount of flash for free. Longevity and reliability suffers, but hey, cheap SSDs!
Ram only gets cheaper by improvements to semiconductor processes, which also can be applied to make flash cheaper. (Big fat asterisk, those processes are very different.) While improvements to flash that allow more levels per cell can't be applied to ram. The price difference between flash and ram will only continue to grow.
Modern flash is quite "analog". The first company to figure out how to reliably store 32 voltage levels per cell (Five bits. PLC?) will make a quick billion.
For other readers wondering what SLC, MLC, TLC, and QLC stand for:
SLC -> Single-Level Cell
MLC -> Multi-Level Cell (now mostly means 2-level cell?)
TLC -> Triple-Level Cell
QLC -> Quad-Level Cell
It seems like a lot of the higher-level cell designs require a '3D' gate architecture, so you might come across that terminology in marketing materials.
- Each MLC cell actually holds one of 4 distinct charge levels, and thus can encode 2 bits. Same for TLC (8 levels, 3 bits) and QLC (16 charge levels to encode 4 bits).
- "3D" when talking about solid-state memory, would usually refer to vertically stacked cells [1], which gives you more cells per square millimeter at the same manufacturing process node. This is orthogonal to xLC.
Beside stacking layers on chips, stacking multiple dies is also used to increase the density per PCB area. (I believe that works for DRAM and flash.) The package you see on the PCB may actually hold tens of silicon slices which themselves each hold tens of layers.
This method can be used until heat dissipation becomes an issue, which may be the reason why CPUs/GPUs are not stacked.
Flash connection protocols (sata, ide) allows much faster evolution independent what's on the other side of interface.
If you have a new flash tech that's 2,3x better in density/speed, you can easily deploy it in current generation of high end server in the next few months.
RAM protocols (DDR2,3,4) must be developed 100% in sync with the CPU vendors. If the major cpu vendors (Intel, AMD, ARM Soc, Qualcomm) decide they don't want your new 2,3x better interface speed/density, you have zero chance to deploy it. It takes years for JEDEC to agree on new memory interface standard. Your new 2,5,10x better tech's deployment is actually depend on your competitors agree to allow it to be the new standard.
Flash can have higher latency as trade off if needed. DDR interface's latency has high impact on the CPU/system benchmark.
CPUs typically support larger DIMM sizes than exist at launch. Having to wait on CPU manufacturers to support larger sizes is probably not an issue. Having an incredibly small market for those larger sizes probably is more of an issue. The Things stored in RAM are replaced all the time. The things stored in flash typically are not replaced, but appended, creating a demand for more.
The DRAM controller is (these days[0]) built directly into the CPU, whereas for flash storage, the NAND controller communicates with the CPU (indirectly) over a standardized interface. So for flash storage, the designers have control over which controller chip they use, and as such can change the NAND technology used at will. They aren't even limited to NAND, if something better comes along. Whereas with RAM, you can't just plug DDR4 into a CPU that only "speaks" DDR3. I think that flexibility is the important distinction.
[0] It used to be that the DRAM controller was on the northbridge, which was a separate chip from the CPU. But for the purposes of performance and power consumption, the tradeoff with flexibility was made (The Athlon 64 was the first [consumer?] CPU to put the memory controller directly on-die, and that was a large part of the reason it crushed the Pentium 4.)
CPUs may, but getting BIOS support on your particular board may be an issue. I've had a number of boards over the years where I had to wait months for the manufacturer to put out an update to support new DIMM sizes correctly.
All things you mention combined only explain a factor up to 4 (probably much less since the complexity increases). With a factor of 2-3 already being realized years ago.
Yup & the most recent flash memory consumer price drops are due to a process shrink plus 3D die stacking, rather than just MLC/TLC.
Stacking can and will be used for DRAM as well but 3D DRAM-based products have not hit high-vol consumer markets yet, so it's currently widening the cost-per-bit gap b/t DRAM & NAND.
Comments
The obvious answer: flash can hold multiple bits per cell and ram can't.
MLC is half as expensive as SLC. TLC is 33% less expensive than MLC. QLC is 25% less expensive than TLC and 75% cheaper than SLC. Not to mention transparent compression algos. As the controllers improve you can get more bits of storage from the same amount of flash for free. Longevity and reliability suffers, but hey, cheap SSDs!
Ram only gets cheaper by improvements to semiconductor processes, which also can be applied to make flash cheaper. (Big fat asterisk, those processes are very different.) While improvements to flash that allow more levels per cell can't be applied to ram. The price difference between flash and ram will only continue to grow.
Modern flash is quite "analog". The first company to figure out how to reliably store 32 voltage levels per cell (Five bits. PLC?) will make a quick billion.
For other readers wondering what SLC, MLC, TLC, and QLC stand for:
SLC -> Single-Level Cell
MLC -> Multi-Level Cell (now mostly means 2-level cell?)
TLC -> Triple-Level Cell
QLC -> Quad-Level Cell
It seems like a lot of the higher-level cell designs require a '3D' gate architecture, so you might come across that terminology in marketing materials.
Sources: https://en.wikipedia.org/wiki/Multi-level_cell and http://www.theregister.co.uk/2016/07/28/qlc_flash_primer/
A bit of trivia:
- Each MLC cell actually holds one of 4 distinct charge levels, and thus can encode 2 bits. Same for TLC (8 levels, 3 bits) and QLC (16 charge levels to encode 4 bits).
- "3D" when talking about solid-state memory, would usually refer to vertically stacked cells [1], which gives you more cells per square millimeter at the same manufacturing process node. This is orthogonal to xLC.
[1] http://www.theregister.co.uk/2013/07/23/sandisk_takes_the_bi...
Beside stacking layers on chips, stacking multiple dies is also used to increase the density per PCB area. (I believe that works for DRAM and flash.) The package you see on the PCB may actually hold tens of silicon slices which themselves each hold tens of layers.
This method can be used until heat dissipation becomes an issue, which may be the reason why CPUs/GPUs are not stacked.
Yep they use TSVs.
Two other factors:
Flash connection protocols (sata, ide) allows much faster evolution independent what's on the other side of interface.
If you have a new flash tech that's 2,3x better in density/speed, you can easily deploy it in current generation of high end server in the next few months.
RAM protocols (DDR2,3,4) must be developed 100% in sync with the CPU vendors. If the major cpu vendors (Intel, AMD, ARM Soc, Qualcomm) decide they don't want your new 2,3x better interface speed/density, you have zero chance to deploy it. It takes years for JEDEC to agree on new memory interface standard. Your new 2,5,10x better tech's deployment is actually depend on your competitors agree to allow it to be the new standard.
Flash can have higher latency as trade off if needed. DDR interface's latency has high impact on the CPU/system benchmark.
CPUs typically support larger DIMM sizes than exist at launch. Having to wait on CPU manufacturers to support larger sizes is probably not an issue. Having an incredibly small market for those larger sizes probably is more of an issue. The Things stored in RAM are replaced all the time. The things stored in flash typically are not replaced, but appended, creating a demand for more.
I think more what the parent post was getting at is perhaps better visualized:
For flash storage, the hierarchy looks like this:
CPU -> standardized interface (PCIe, SATA) -> Controller Chip -> NAND
For DRAM, it looks like this: CPU -> DRAM
The DRAM controller is (these days[0]) built directly into the CPU, whereas for flash storage, the NAND controller communicates with the CPU (indirectly) over a standardized interface. So for flash storage, the designers have control over which controller chip they use, and as such can change the NAND technology used at will. They aren't even limited to NAND, if something better comes along. Whereas with RAM, you can't just plug DDR4 into a CPU that only "speaks" DDR3. I think that flexibility is the important distinction.
[0] It used to be that the DRAM controller was on the northbridge, which was a separate chip from the CPU. But for the purposes of performance and power consumption, the tradeoff with flexibility was made (The Athlon 64 was the first [consumer?] CPU to put the memory controller directly on-die, and that was a large part of the reason it crushed the Pentium 4.)
CPUs may, but getting BIOS support on your particular board may be an issue. I've had a number of boards over the years where I had to wait months for the manufacturer to put out an update to support new DIMM sizes correctly.
Make those protocols NVME, PCIe and SATA. Don't think I've seen an IDE flash drive yet ;)
CompactFlash (CF) is effectively IDE/PATA.
"MLC is half as expensive as SLC. TLC is 33% less expensive than MLC. QLC is 25% less expensive than TLC and 75% cheaper than SLC."
visualized: http://i.imgur.com/niinuEz.png
All things you mention combined only explain a factor up to 4 (probably much less since the complexity increases). With a factor of 2-3 already being realized years ago.
Yup & the most recent flash memory consumer price drops are due to a process shrink plus 3D die stacking, rather than just MLC/TLC.
Stacking can and will be used for DRAM as well but 3D DRAM-based products have not hit high-vol consumer markets yet, so it's currently widening the cost-per-bit gap b/t DRAM & NAND.