For other readers wondering what SLC, MLC, TLC, and QLC stand for:
SLC -> Single-Level Cell
MLC -> Multi-Level Cell (now mostly means 2-level cell?)
TLC -> Triple-Level Cell
QLC -> Quad-Level Cell
It seems like a lot of the higher-level cell designs require a '3D' gate architecture, so you might come across that terminology in marketing materials.
- Each MLC cell actually holds one of 4 distinct charge levels, and thus can encode 2 bits. Same for TLC (8 levels, 3 bits) and QLC (16 charge levels to encode 4 bits).
- "3D" when talking about solid-state memory, would usually refer to vertically stacked cells [1], which gives you more cells per square millimeter at the same manufacturing process node. This is orthogonal to xLC.
Beside stacking layers on chips, stacking multiple dies is also used to increase the density per PCB area. (I believe that works for DRAM and flash.) The package you see on the PCB may actually hold tens of silicon slices which themselves each hold tens of layers.
This method can be used until heat dissipation becomes an issue, which may be the reason why CPUs/GPUs are not stacked.
Comments
For other readers wondering what SLC, MLC, TLC, and QLC stand for:
SLC -> Single-Level Cell
MLC -> Multi-Level Cell (now mostly means 2-level cell?)
TLC -> Triple-Level Cell
QLC -> Quad-Level Cell
It seems like a lot of the higher-level cell designs require a '3D' gate architecture, so you might come across that terminology in marketing materials.
Sources: https://en.wikipedia.org/wiki/Multi-level_cell and http://www.theregister.co.uk/2016/07/28/qlc_flash_primer/
A bit of trivia:
- Each MLC cell actually holds one of 4 distinct charge levels, and thus can encode 2 bits. Same for TLC (8 levels, 3 bits) and QLC (16 charge levels to encode 4 bits).
- "3D" when talking about solid-state memory, would usually refer to vertically stacked cells [1], which gives you more cells per square millimeter at the same manufacturing process node. This is orthogonal to xLC.
[1] http://www.theregister.co.uk/2013/07/23/sandisk_takes_the_bi...
Beside stacking layers on chips, stacking multiple dies is also used to increase the density per PCB area. (I believe that works for DRAM and flash.) The package you see on the PCB may actually hold tens of silicon slices which themselves each hold tens of layers.
This method can be used until heat dissipation becomes an issue, which may be the reason why CPUs/GPUs are not stacked.
Yep they use TSVs.