The subheading of the question was never addressed—"how do we get all of that information compacted onto that ever shrinking chip?"
That's always been the biggest mystery to me: what are chip manufacturers doing differently with each of these "process nodes" that makes them able to do photolithography at slightly smaller scales, but with the scale only shrinking a little bit per five-year-interval?
Naively, I'd expect a process like photolithography to be mostly scale-invariant (you can lens a mask down to whatever size you like) down to a size where it hits a wall due to quantum effects. So when photolithography was invented, why didn't chips suddenly jump from 100um to 100nm scale?
why didn't chips suddenly jump from 100um to 100nm scale?
Another point is that Moore's Law is at least partially self fulfilling. If you are a Chip Fabrication company you need to spend money to make new technologies, the smaller you want things to be the more money you have to spend. You could spend a comparatively huge amount of money and leap ahead of all of the competition, but then you'd have to charge more than the competition for your services. All of your customers are expecting things to progress according to Moore's law, so they won't be prepared to spend the extra money. I suppose ideally you want to be just ahead of the competition, not way ahead. I hope that makes sense, I found that hard to articulate.
why didn't chips suddenly jump from 100um to 100nm scale?
Manufacturing processes. As you go to smaller scales, the investment required to do so increases, and the error rate as well. When you produce millions of units you want to have a low reject rate, and your process needs to be fully controlled. That's why there's always a gap between what's technically possible and what makes sense in a industrial context.
There is a substantial amount of detail to be added, but if you just want to skim through some industry documentation the International Semiconductor Roadmap for Semiconductors describes a lot of the challenges involved in producing leading edge process products. This is from the working group that a lot of our companies participate in to coordinate what everybody will need from tool vendors and by when (e.g. when everybody wants to start pushing for 450mm wafers all the tools need to already be able to accommodate a larger wafer).
Photolithography is very difficult to accomplish when feature size is smaller than the wavelength of light used. They have to do all sorts of crazy things with interference patterns to get below 200nm. It's amazing that it has progressed to 22nm
Comments
The subheading of the question was never addressed—"how do we get all of that information compacted onto that ever shrinking chip?"
That's always been the biggest mystery to me: what are chip manufacturers doing differently with each of these "process nodes" that makes them able to do photolithography at slightly smaller scales, but with the scale only shrinking a little bit per five-year-interval?
Naively, I'd expect a process like photolithography to be mostly scale-invariant (you can lens a mask down to whatever size you like) down to a size where it hits a wall due to quantum effects. So when photolithography was invented, why didn't chips suddenly jump from 100um to 100nm scale?
Another point is that Moore's Law is at least partially self fulfilling. If you are a Chip Fabrication company you need to spend money to make new technologies, the smaller you want things to be the more money you have to spend. You could spend a comparatively huge amount of money and leap ahead of all of the competition, but then you'd have to charge more than the competition for your services. All of your customers are expecting things to progress according to Moore's law, so they won't be prepared to spend the extra money. I suppose ideally you want to be just ahead of the competition, not way ahead. I hope that makes sense, I found that hard to articulate.
why didn't chips suddenly jump from 100um to 100nm scale?
Many things, among them the precision of the available machinery of the time - aligning the masks accurately is very important, for example.
The newest 1Xnm processes require special techniques involving diffraction, as the wavelength of light becomes much greater than the feature size.
http://en.wikipedia.org/wiki/Multiple_patterning
Manufacturing processes. As you go to smaller scales, the investment required to do so increases, and the error rate as well. When you produce millions of units you want to have a low reject rate, and your process needs to be fully controlled. That's why there's always a gap between what's technically possible and what makes sense in a industrial context.
There is a substantial amount of detail to be added, but if you just want to skim through some industry documentation the International Semiconductor Roadmap for Semiconductors describes a lot of the challenges involved in producing leading edge process products. This is from the working group that a lot of our companies participate in to coordinate what everybody will need from tool vendors and by when (e.g. when everybody wants to start pushing for 450mm wafers all the tools need to already be able to accommodate a larger wafer).
http://www.itrs.net/Links/2013ITRS/Summary2013.htm
The papers themselves as well as the models are all very interesting if a bit occasionally dry.
Photolithography is very difficult to accomplish when feature size is smaller than the wavelength of light used. They have to do all sorts of crazy things with interference patterns to get below 200nm. It's amazing that it has progressed to 22nm