Comment on PlayStation 3 Architecture (2021)parentComments−maximilianburke10moIt's definitely not registers; the SPEs had 128 128-bit registers each.In some ways it's like cache, it has the latency of L1 cache (6 cycles), but it's fully deterministic in terms of access.
Comments
It's definitely not registers; the SPEs had 128 128-bit registers each.
In some ways it's like cache, it has the latency of L1 cache (6 cycles), but it's fully deterministic in terms of access.