Comment on PlayStation 3 Architecture (2021)parentComments−otabdeveloper410mowhy don't we have that on other cpus?We do, it's called "cache" or "registers".−maximilianburke10moIt's definitely not registers; the SPEs had 128 128-bit registers each.In some ways it's like cache, it has the latency of L1 cache (6 cycles), but it's fully deterministic in terms of access.−lepicz10moas a programmer you have (almost) no control over cache. that's not what i meant.registers ok, but i want at least one megabyte of them :)
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We do, it's called "cache" or "registers".
It's definitely not registers; the SPEs had 128 128-bit registers each.
In some ways it's like cache, it has the latency of L1 cache (6 cycles), but it's fully deterministic in terms of access.
as a programmer you have (almost) no control over cache. that's not what i meant.
registers ok, but i want at least one megabyte of them :)