If SSD logic boards are any indication, devices with fewer chips frequently have lower read/write speeds, as they're not using all the lanes on the controller.
I'm thinking this would be the case as well on a tablet, unless the flash is in a bus topology already.
> I'm thinking this would be the case as well on a tablet, unless the flash is in a bus topology already.
There is no speed difference between 1 or 2 chips in this context, they are just treated as separate banks and mapped to different memory addresses controlled by the flash memory controller in the SoC.
Comments
If SSD logic boards are any indication, devices with fewer chips frequently have lower read/write speeds, as they're not using all the lanes on the controller.
I'm thinking this would be the case as well on a tablet, unless the flash is in a bus topology already.
> I'm thinking this would be the case as well on a tablet, unless the flash is in a bus topology already.
There is no speed difference between 1 or 2 chips in this context, they are just treated as separate banks and mapped to different memory addresses controlled by the flash memory controller in the SoC.