That SiFive FE-310 chip on the HiFive1 on 180nm in 2016 was a 32 bit 1 instruction per cycle 5-stage pipelined CPU running at 320 MHz.
That's way more than typical microcontrollers in embedded uses even today -- 24 or 48 MHz is very common for e.g. Cortex M0+ and you seldom find over 180 MHz for Cortex M3/M4. Those (or competitors) make up the vast bulk of the market.
That 320 MHz is with automated placement and routing with a standard cell library. Back when 180nm was new both Intel (Pentium III) and Motorola (G4) were getting 1 GHz or a bit more out of it with a lot of engineers using a much more manual process.
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That SiFive FE-310 chip on the HiFive1 on 180nm in 2016 was a 32 bit 1 instruction per cycle 5-stage pipelined CPU running at 320 MHz.
That's way more than typical microcontrollers in embedded uses even today -- 24 or 48 MHz is very common for e.g. Cortex M0+ and you seldom find over 180 MHz for Cortex M3/M4. Those (or competitors) make up the vast bulk of the market.
That 320 MHz is with automated placement and routing with a standard cell library. Back when 180nm was new both Intel (Pentium III) and Motorola (G4) were getting 1 GHz or a bit more out of it with a lot of engineers using a much more manual process.