I worked with some chip design and verification folks.
They were very tolerant of slow results, waiting for licenses or infrastructure. Their processes were just built around those constraints. They didn't seem to have interest in removing them.
As an impatient software developer it was very interesting.
Project cycles are long. We are typically doing 1 tapeout/quarter. Chips are incredibly complex, and the physical design is a by definition slow process. Of couse everyone wants quicker tools/turnaround but bottleneck isn't RTL development, physical design and verification is.
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I worked with some chip design and verification folks. They were very tolerant of slow results, waiting for licenses or infrastructure. Their processes were just built around those constraints. They didn't seem to have interest in removing them.
As an impatient software developer it was very interesting.
Project cycles are long. We are typically doing 1 tapeout/quarter. Chips are incredibly complex, and the physical design is a by definition slow process. Of couse everyone wants quicker tools/turnaround but bottleneck isn't RTL development, physical design and verification is.
Yeah, our team has experience in both hardware and software. DV engineers have a really hard time and we're trying to make it better.