Might be useful in OS kernel programming, when threads are not available. Like in IRQs, etc.
My state machines in those contexts are such beasts sometimes, when you have to account for different combinations of DMA progress/completion, etc. Sometimes the hardware limitations you need to handle in software makes you really bang your head to the wall...
Thread-per-core architectures might bring this back to the fore. Especially with things like GPUDirect, StorageDirect and all the DMA engines being slowly integrated into everything.
If you have some taskgraph that is static or predictible (think closed-loop control) and you need low latency this might be your best option.
Comments
Might be useful in OS kernel programming, when threads are not available. Like in IRQs, etc.
My state machines in those contexts are such beasts sometimes, when you have to account for different combinations of DMA progress/completion, etc. Sometimes the hardware limitations you need to handle in software makes you really bang your head to the wall...
Thread-per-core architectures might bring this back to the fore. Especially with things like GPUDirect, StorageDirect and all the DMA engines being slowly integrated into everything.
If you have some taskgraph that is static or predictible (think closed-loop control) and you need low latency this might be your best option.
Would love to talk to you more about this, do you have an email address I can get to you at?