I can't say I have a great deal of knowledge on the subject, but isn't doping done by surface diffusion? How would the transistors be created in the interior of the volume?
I do not think this would be practical but at least in principle one could build 10,000 by 10,000 transistors in a layer, deposit some material on top, and then start building the next layer. Repeat 10,000 times. When you are done, you would have a cube of maybe about 2 mm side length containing a trillion transistors.
It would be somewhat like 3D printing, you repeat a fundamentally two dimensional process along a third dimension over and over again. And to some extend this is exactly how chips are currently made, in many steps and layers to build up the different transistor parts and the interconnect.
But it could certainly be the case that this is not practical and one would have to look for fundamentally different processes to build up such structures, maybe some self-assembly process. But I really have no clue if and what has been considered, that is why I asked about it in the first place.
The reason this is not done is that you want the channel of your transistors to consist of a fully epitaxial layer (that is, an entirely clean and regular lattice of atoms) of silicon for best performance. It's not possible to deposit such layers, they are only formed during crystal formation when the silicon ingot is formed.
3d-nand is built sort of like you propose (except that instead of 10000 vertically stacked layers, they are up to a few hundred), but they get away with using sucky polysilicon for their channel because only a very small part of the chip is ever lit at the same time, so it's okay for the channels to leak like a sieve.
Well, many CPU designs are made so that a few defects can be worked around at the cost of a bit of performance. It might be possible to do something like that and include a few spare logic units on each layer to get a decent yield.
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I can't say I have a great deal of knowledge on the subject, but isn't doping done by surface diffusion? How would the transistors be created in the interior of the volume?
I do not think this would be practical but at least in principle one could build 10,000 by 10,000 transistors in a layer, deposit some material on top, and then start building the next layer. Repeat 10,000 times. When you are done, you would have a cube of maybe about 2 mm side length containing a trillion transistors.
It would be somewhat like 3D printing, you repeat a fundamentally two dimensional process along a third dimension over and over again. And to some extend this is exactly how chips are currently made, in many steps and layers to build up the different transistor parts and the interconnect.
But it could certainly be the case that this is not practical and one would have to look for fundamentally different processes to build up such structures, maybe some self-assembly process. But I really have no clue if and what has been considered, that is why I asked about it in the first place.
The reason this is not done is that you want the channel of your transistors to consist of a fully epitaxial layer (that is, an entirely clean and regular lattice of atoms) of silicon for best performance. It's not possible to deposit such layers, they are only formed during crystal formation when the silicon ingot is formed.
3d-nand is built sort of like you propose (except that instead of 10000 vertically stacked layers, they are up to a few hundred), but they get away with using sucky polysilicon for their channel because only a very small part of the chip is ever lit at the same time, so it's okay for the channels to leak like a sieve.
I suspect that there is a defect probability per mask layer. If so, your 10,000 layer cube is going to have a very low yield.
Well, many CPU designs are made so that a few defects can be worked around at the cost of a bit of performance. It might be possible to do something like that and include a few spare logic units on each layer to get a decent yield.