The reason this is not done is that you want the channel of your transistors to consist of a fully epitaxial layer (that is, an entirely clean and regular lattice of atoms) of silicon for best performance. It's not possible to deposit such layers, they are only formed during crystal formation when the silicon ingot is formed.
3d-nand is built sort of like you propose (except that instead of 10000 vertically stacked layers, they are up to a few hundred), but they get away with using sucky polysilicon for their channel because only a very small part of the chip is ever lit at the same time, so it's okay for the channels to leak like a sieve.
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The reason this is not done is that you want the channel of your transistors to consist of a fully epitaxial layer (that is, an entirely clean and regular lattice of atoms) of silicon for best performance. It's not possible to deposit such layers, they are only formed during crystal formation when the silicon ingot is formed.
3d-nand is built sort of like you propose (except that instead of 10000 vertically stacked layers, they are up to a few hundred), but they get away with using sucky polysilicon for their channel because only a very small part of the chip is ever lit at the same time, so it's okay for the channels to leak like a sieve.