The concept of WOM isn't completely pointless for non von Neumann architectures, and could even be useful for von Neumann-esque SPMD or MPMD systolic array (http://en.wikipedia.org/wiki/Systolic_array) architectures that have strict execution models forced in the core to core wiring. While not completely free form, you would still have instructions and data being stored in the same space, it would be only readable by the individual PU is corresponds to. That PU would not write-back to that same memory, and instead could only write to an adjacent PU's memory, which then would only be readable (and not writable) by that next PU in the line.
I've been wanting to implement such an architecture on an FPGA for a while now... may do so over this winter break.
Comments
The concept of WOM isn't completely pointless for non von Neumann architectures, and could even be useful for von Neumann-esque SPMD or MPMD systolic array (http://en.wikipedia.org/wiki/Systolic_array) architectures that have strict execution models forced in the core to core wiring. While not completely free form, you would still have instructions and data being stored in the same space, it would be only readable by the individual PU is corresponds to. That PU would not write-back to that same memory, and instead could only write to an adjacent PU's memory, which then would only be readable (and not writable) by that next PU in the line.
I've been wanting to implement such an architecture on an FPGA for a while now... may do so over this winter break.
How do you implement this kind of thing in an FPGA ? It sounds intriguing.