This is something I'm interested in discovering as well. I view most of these developments as modular components that could be used in conjunction with existing processor pipelines. For instance, with these 'neural' chips, I could imagine an existing processor querying the neural chip to look for particular activation patterns. Though I'm not too sure on the language one would use to specify which patterns to look for... Perhaps you could extract the parameters from the neural chip itself through a learning process, which you'd then use to bootstrap the process a bit and know what to look for? I'd imagine a lot of formal research is still needed here.
Neat developments, excited to see how they shake out.
One possibility is to use the neuromorphic chips as souped-up branch predictors -- instead of predicting one bit, as in a branch predictor, predict all bits relevant for speculative execution. This can effect large-scale automatic parallelization.
Comments
This is something I'm interested in discovering as well. I view most of these developments as modular components that could be used in conjunction with existing processor pipelines. For instance, with these 'neural' chips, I could imagine an existing processor querying the neural chip to look for particular activation patterns. Though I'm not too sure on the language one would use to specify which patterns to look for... Perhaps you could extract the parameters from the neural chip itself through a learning process, which you'd then use to bootstrap the process a bit and know what to look for? I'd imagine a lot of formal research is still needed here.
Neat developments, excited to see how they shake out.
One possibility is to use the neuromorphic chips as souped-up branch predictors -- instead of predicting one bit, as in a branch predictor, predict all bits relevant for speculative execution. This can effect large-scale automatic parallelization.
See this paper at ASPLOS '14 for details:
http://hips.seas.harvard.edu/content/asc-automatically-scala...