Comment on Why Registers Are Fast and RAM Is SlowComments−twoodfin12yDo any current ARM implementations do register renaming over a physical register set larger than the architected set?Obviously Intel has been doing this for a while: Haswell has something like 168 integer registers, while the x86-64 ISA only exposes 16.EDIT: Some Googling tells me that at least the Cortex-A9 mapped 32 architectural registers to 56 physical: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc....−Symmetry12yBasically anybody doing out of order execution these days is going to be be doing register remapping at some level.
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Do any current ARM implementations do register renaming over a physical register set larger than the architected set?
Obviously Intel has been doing this for a while: Haswell has something like 168 integer registers, while the x86-64 ISA only exposes 16.
EDIT: Some Googling tells me that at least the Cortex-A9 mapped 32 architectural registers to 56 physical: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc....
Basically anybody doing out of order execution these days is going to be be doing register remapping at some level.