There is also an issue of FastISel not supporting the full LLVM IR, so if you depend on FastISel for fast JIT, you basically need to design LLVM IR generation around that, limiting yourself to undocumented, unspecified, and ever changing subset of LLVM IR. Which can be done, but not very pleasant.
So I guess I disagree.
There are known good solutions to this problem.
Yes, it's definitely some work actually writing the code right, but it's not like this is a problem that requires engineering brand new solutions.
It just requires a good engineer and some time.
I consider that "simple", as on the scale of "engineering complexity", it would be simple, even though on the scale of "engineering time" it may take longer.
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There is also an issue of FastISel not supporting the full LLVM IR, so if you depend on FastISel for fast JIT, you basically need to design LLVM IR generation around that, limiting yourself to undocumented, unspecified, and ever changing subset of LLVM IR. Which can be done, but not very pleasant.
Right, but unlike GCC, this is not an architectural issue, but a simple implementation issue that could be fixed.
It's an implementation issue, but it is far from simple.
So I guess I disagree. There are known good solutions to this problem. Yes, it's definitely some work actually writing the code right, but it's not like this is a problem that requires engineering brand new solutions. It just requires a good engineer and some time.
I consider that "simple", as on the scale of "engineering complexity", it would be simple, even though on the scale of "engineering time" it may take longer.