If DRAM gets the ability to modify itself (computations), it doesn't eliminate the cache layer between the CPU and DRAM. For the CPU to see updated DRAM values it has to bring in the DRAM to cache. Now, if that's a large amount of data, like 1MByte of computations, it's worth it, but for a couple of source/destination addresses in code, probably not. There's also the fact instruction and data caches are separate.
Now, if the RAM in the CPU cache gets computational ability as well, that all changes, but not sure really that would be better than SIMD/SEE/AVX stuff or expanding what can be done with the new tile registers Intel's rolling out.
Comments
If DRAM gets the ability to modify itself (computations), it doesn't eliminate the cache layer between the CPU and DRAM. For the CPU to see updated DRAM values it has to bring in the DRAM to cache. Now, if that's a large amount of data, like 1MByte of computations, it's worth it, but for a couple of source/destination addresses in code, probably not. There's also the fact instruction and data caches are separate.
Now, if the RAM in the CPU cache gets computational ability as well, that all changes, but not sure really that would be better than SIMD/SEE/AVX stuff or expanding what can be done with the new tile registers Intel's rolling out.