Can I confess I've never quite wrapped my head around the application of the 'inhibit' line in this?
If a write cycle is just a read cycle with a) a reversed polarity and b) you don't care about the contents of the sense line - I don't get why current coincidence is sufficient during the read cycle, but not during the write cycle?
Every description of this I've ever read, sound like inhibit and current coincidence solve the same problem - but have never left me clear on why we need to solve it twice.
The current coincidence is used to select a specific bit / core. Except it selects the same bit in every bank.
Bytes or larger words are made by stacking multiple banks together (18 in the articles case) All 18 bits would be driven in parallel by the driver over the X/Y wires to produce a coherent 18 bit value at the same moment.
The inhibit bit was so you could select which of those 18 bits (in separate banks) would be switched back to a 1, not selecting which bit across the entire bank.
ahh - I see where my dots weren't connecting, then.
I pictured having a current driver on each plane, so the data bits coming in would be enable bits for the current drivers. Which obviously means 18xQty current drivers.
I think you're describing having one big current driver for the whole job, and then data bits drive the inhibits to counter them.
I guess I'm looking through too modern a lens - pumping 18*600mA into the write cycle, plus (up to 18)*600mA into the inhibit, sounds insane to me (hitting 20A for a write) - but I can see that multiplying the current drivers may have sounded nuts in the 50s.
There are different ways of implementing core memory. The "traditional" way uses the inhibit line. The module I examined uses a "2½D" approach, which is what you originally pictured: separate current drivers for each bit and no inhibit line.
Comments
Can I confess I've never quite wrapped my head around the application of the 'inhibit' line in this?
If a write cycle is just a read cycle with a) a reversed polarity and b) you don't care about the contents of the sense line - I don't get why current coincidence is sufficient during the read cycle, but not during the write cycle?
Every description of this I've ever read, sound like inhibit and current coincidence solve the same problem - but have never left me clear on why we need to solve it twice.
The current coincidence is used to select a specific bit / core. Except it selects the same bit in every bank.
Bytes or larger words are made by stacking multiple banks together (18 in the articles case) All 18 bits would be driven in parallel by the driver over the X/Y wires to produce a coherent 18 bit value at the same moment.
The inhibit bit was so you could select which of those 18 bits (in separate banks) would be switched back to a 1, not selecting which bit across the entire bank.
ahh - I see where my dots weren't connecting, then.
I pictured having a current driver on each plane, so the data bits coming in would be enable bits for the current drivers. Which obviously means 18xQty current drivers.
I think you're describing having one big current driver for the whole job, and then data bits drive the inhibits to counter them.
I guess I'm looking through too modern a lens - pumping 18*600mA into the write cycle, plus (up to 18)*600mA into the inhibit, sounds insane to me (hitting 20A for a write) - but I can see that multiplying the current drivers may have sounded nuts in the 50s.
There are different ways of implementing core memory. The "traditional" way uses the inhibit line. The module I examined uses a "2½D" approach, which is what you originally pictured: separate current drivers for each bit and no inhibit line.