Bro there's an IANUS acronym in this article and nobody has said anything. Shame on you all
PIM (XBM, ZAM, etc) are all cope. This 600GB of throughput is ~4.5x higher than the 130 you get from LPDDR5X on a 128 bit bus yet their deltas are only 2.2-3x? I just don't see this being a corner worth cutting over simply paying the cost of a wider bus. Think of all the fun new rowhammer shit this will be able to do to itself
Bro, I’m not following. Can you elaborate? - concretely PIM is cope. And the argument that this is bad because rowhammer and how a wider bus would be better.
Comments
Bro there's an IANUS acronym in this article and nobody has said anything. Shame on you all
PIM (XBM, ZAM, etc) are all cope. This 600GB of throughput is ~4.5x higher than the 130 you get from LPDDR5X on a 128 bit bus yet their deltas are only 2.2-3x? I just don't see this being a corner worth cutting over simply paying the cost of a wider bus. Think of all the fun new rowhammer shit this will be able to do to itself
Bro, I’m not following. Can you elaborate? - concretely PIM is cope. And the argument that this is bad because rowhammer and how a wider bus would be better.
Explain rank 3 memory subtimings to me without using LLMs and I'll humor you