Security-partition switches that carefully reset all shared micro-architectural state, while making switch times completely deterministic, and in particular, independent of previous execution history.
I'm afraid it means clearing all caches at each context switch. The performance penalty is really high.
Not all caches are cleared. There are some clever techniques to partition off-core caches (i.e. the L3) as part of the isolation boundaries enforced by the kernel. What I think is particularly exciting is that a new RISCV64 instruction to clear microarchitectural state is in the process of being standardised! So I'm hopeful that, while it should not be ignored, the performance penalty will not be too high.
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Security-partition switches that carefully reset all shared micro-architectural state, while making switch times completely deterministic, and in particular, independent of previous execution history.
I'm afraid it means clearing all caches at each context switch. The performance penalty is really high.
Not all caches are cleared. There are some clever techniques to partition off-core caches (i.e. the L3) as part of the isolation boundaries enforced by the kernel. What I think is particularly exciting is that a new RISCV64 instruction to clear microarchitectural state is in the process of being standardised! So I'm hopeful that, while it should not be ignored, the performance penalty will not be too high.