Well even in deep pipelined FPUs (I'm thinking Weitek 1167 for example), the "divide" instruction is microcoded ... this chip had a full IEEE P764 64-bit single cycle barrel shifting MAC ... but divide was built via a special "3-bit and guess" kind of long division that was microcoded. MAYBE someone has built a hardcoded divider these days - but that would be a waste if good transistors in typical instruction mix.
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Yeah — even ARM2 has no divide, as far as I recall from my days with an A310.
Well even in deep pipelined FPUs (I'm thinking Weitek 1167 for example), the "divide" instruction is microcoded ... this chip had a full IEEE P764 64-bit single cycle barrel shifting MAC ... but divide was built via a special "3-bit and guess" kind of long division that was microcoded. MAYBE someone has built a hardcoded divider these days - but that would be a waste if good transistors in typical instruction mix.