I was aware that some architectures had distinct floating point registers
Most ISAs do.
On x86 and arm scalar and FP registers are separate, it's just that they overlap FP and SIMD registers.
On RISC-V there are three separate register files for scalar, FP and SIMD. Although you can overlap scalar and FP in some minimal embedded configurations.
D'oh. I'm old enough to have written software which needs to care about the i387 FPU and yet here I am acting as though the floating point instructions use the ordinary scalar registers. Worse, I have a window open where I'm writing toy software that doesn't compile because it is asking to do an FPU operation on a GPR and rather than fix that, which would remind me that this can't work, I decided to alt-tab to HN and make the exact same mistake.
Comments
Most ISAs do.
On x86 and arm scalar and FP registers are separate, it's just that they overlap FP and SIMD registers.
On RISC-V there are three separate register files for scalar, FP and SIMD. Although you can overlap scalar and FP in some minimal embedded configurations.
D'oh. I'm old enough to have written software which needs to care about the i387 FPU and yet here I am acting as though the floating point instructions use the ordinary scalar registers. Worse, I have a window open where I'm writing toy software that doesn't compile because it is asking to do an FPU operation on a GPR and rather than fix that, which would remind me that this can't work, I decided to alt-tab to HN and make the exact same mistake.