Arguably the ECL was just digging themselves deeper, the real failure was upper management fighting any suggestion that VAX has played out and should be replaced. EDIT: Then there's the infighting between "big ECL VAX" and everyone else, which was very resource draining.
All the CISC vs RISC literature that brought us the memes about "expensive decode" talked mainly about VAX and m68k as CISC. By comparison, x86 was always closer to RISC designs if only by accident of limited resources of 8086. Even NVAX had, IIRC, ridiculously large microcode - and with orthogonal ISA you had to accept every instruction could balloon info long multi step microcode loop before you even start feeding the ALU.
Making such complex ISA fast was harder than x86 which in 1990s, with NVAX requiring pipelined decoder in Ibox to feed the rest and non trivially depending on possibility of Mbox (memory) requests from I and E boxes to overlap between two instructions to feed the beast.
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Arguably the ECL was just digging themselves deeper, the real failure was upper management fighting any suggestion that VAX has played out and should be replaced. EDIT: Then there's the infighting between "big ECL VAX" and everyone else, which was very resource draining.
All the CISC vs RISC literature that brought us the memes about "expensive decode" talked mainly about VAX and m68k as CISC. By comparison, x86 was always closer to RISC designs if only by accident of limited resources of 8086. Even NVAX had, IIRC, ridiculously large microcode - and with orthogonal ISA you had to accept every instruction could balloon info long multi step microcode loop before you even start feeding the ALU.
Making such complex ISA fast was harder than x86 which in 1990s, with NVAX requiring pipelined decoder in Ibox to feed the rest and non trivially depending on possibility of Mbox (memory) requests from I and E boxes to overlap between two instructions to feed the beast.