gdevic on Show HN: A nibble-oriented CPU in Verilog to build a scientific calculator

Comment on Show HN: A nibble-oriented CPU in Verilog to build a scientific calculator parent

That. I blatantly "stole" those from Z80 since they are elegant and effective. I have BF (flag) that gets set in ALU when the result is > 9, then DAA/DAS that add 6 or 10 (the latter wraps around as -6 since registers are 4-bit wide).

     12'b0000_0000_001?: begin : instr_daas    // DAA, DAS
       if (flags[BF_BIT])
         rx[0] <= rx[0] + (op_is_daa ? 4'd6 : 4'd10);
       flags[CF_BIT] <= flags[BF_BIT];
       state <= FETCH;
     end : instr_daas

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