If anyone is interested, at https://sonic-rv.ics.jku.at/ we built an educational platform for web-based simulation and visualization of RISC-V processor architectures.
Our pipeline visualization is reconstructed from real RTL traces (you can run your on programs which are simulated using GHDL).
Under examples you can find some different architectures based on the Harris&Harris book on computer architecture.
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If anyone is interested, at https://sonic-rv.ics.jku.at/ we built an educational platform for web-based simulation and visualization of RISC-V processor architectures.
Our pipeline visualization is reconstructed from real RTL traces (you can run your on programs which are simulated using GHDL).
Under examples you can find some different architectures based on the Harris&Harris book on computer architecture.