All RISC ISAs are basically the same thing as far as compiler optimisation is concerned, and there is 40 years of work into that already.
I can't see any reason why the father of Zen and the designer of the M1 can't make a core for the simpler RISC-V ISA with basically the same (or better) µarch than the M1.
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All RISC ISAs are basically the same thing as far as compiler optimisation is concerned, and there is 40 years of work into that already.
I can't see any reason why the father of Zen and the designer of the M1 can't make a core for the simpler RISC-V ISA with basically the same (or better) µarch than the M1.