Is there a reason you wired MOSI and MISO together with a resistor instead of setting the SPI_SIO bit in the ESP32C6's SPI controller? The reference manual[1] says that bit enables "3-line half-duplex communication, where MOSI and MISO signals share the same pin" (page 866). I'm not sure if it's suitable, since the half-duplex mode (see section 28.5.8.4) seems to be designed mainly for talking to SPI flash chips.
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Author here, if anyone has deeper questions
Is there a reason you wired MOSI and MISO together with a resistor instead of setting the SPI_SIO bit in the ESP32C6's SPI controller? The reference manual[1] says that bit enables "3-line half-duplex communication, where MOSI and MISO signals share the same pin" (page 866). I'm not sure if it's suitable, since the half-duplex mode (see section 28.5.8.4) seems to be designed mainly for talking to SPI flash chips.
[1] https://www.espressif.com/sites/default/files/documentation/...
Good idea - I can take this to the developers of Toit lang https://toitlang.org/ which is the stack I'm using and is built atop of ESP-IDF
Proud of your work! Keep it up
Thank you for saying so! 1 month until this one hits the Google Graveyard; Kevo smart locks are next, who knows what comes after
Well done, seems like a very challenging project!