In academia people use general purpose languages (Notably C++ dialects) for FPGA design quite a lot. And there's definitely a glut of papers published on the development of such "High Level Synthesis" tools.
In order to use the FPGA efficiently you need to first pipeline the logic deeply, but then also be able to fill that pipeline.
But in my opinion there is just too much of an impedance mismatch between the "do one thing and then the next" style of imperative code, and the "everything everywhere all at once" way in which FPGAs actually work.
And well, here's my plug for my language that gets close to HLS in terms of syntactic ease, while still retaining full control over the generated hardware: https://github.com/pc2/sus-compiler
By explicitly keeping track of pipelining in submodules the compiler automatically balances the pipelines your create, and in addition, you can write modules that respond to the pipeline distance between their ports, and infer their parameters based on that. That fixes one of the most error-prone activities when designing hardware in SV or other languages.
I worked in industry, trying to fit video processing algorithms and filter banks to FPGAs, about a decade ago, so my memories are a bit fuzzy.
The thing about FPGAs is that they are wildly expensive, getting exponentially more so the more you move up the product pallette. They also have a ton of special function blocks (DPRAM, multipliers, shift registers etc), that work differently from vendor to vendor, and even between generations.
Even with HDLs you had to options - either read all the datasheet, the layout and mix of components, and plan your design to fit the hardware - or just wing it and write down what you wanted, and hope for the best - in the latter scenario, the synthesis tool had to figure out how to fit your design best to the hardware, which even if you were mindful of how the chip worked, was still a hit and miss.
When you work in industry and either every cent counts, or you have to design for a fixed target, and somehow you're in the good graces of tooling, finding that changing a small thing suddenly makes your design 3x as big and half as fast is not acceptable.
HLS was this, but on steroids - you never knew what you were going to get, sometimes it worked well, sometimes not at all.
I'm sure tooling has evolved back then but I'd still guess spending the extra engineering effort is often well worth it when your chips cost five figures.
Yup, HLS is ridiculously fickle in that regard. In our lab we had the case that swapping out a C-style array T[] for a C++ std::array 10x-ed our resource consumption with no explanation.
And also the general problem of scribing resource use to the different components isn't easy, because thz way control flow is structured heavily alters that
Of course, that's what I'm trying to fix with SUS :p
Comments
In academia people use general purpose languages (Notably C++ dialects) for FPGA design quite a lot. And there's definitely a glut of papers published on the development of such "High Level Synthesis" tools.
In order to use the FPGA efficiently you need to first pipeline the logic deeply, but then also be able to fill that pipeline.
But in my opinion there is just too much of an impedance mismatch between the "do one thing and then the next" style of imperative code, and the "everything everywhere all at once" way in which FPGAs actually work.
And well, here's my plug for my language that gets close to HLS in terms of syntactic ease, while still retaining full control over the generated hardware: https://github.com/pc2/sus-compiler
By explicitly keeping track of pipelining in submodules the compiler automatically balances the pipelines your create, and in addition, you can write modules that respond to the pipeline distance between their ports, and infer their parameters based on that. That fixes one of the most error-prone activities when designing hardware in SV or other languages.
I worked in industry, trying to fit video processing algorithms and filter banks to FPGAs, about a decade ago, so my memories are a bit fuzzy.
The thing about FPGAs is that they are wildly expensive, getting exponentially more so the more you move up the product pallette. They also have a ton of special function blocks (DPRAM, multipliers, shift registers etc), that work differently from vendor to vendor, and even between generations.
Even with HDLs you had to options - either read all the datasheet, the layout and mix of components, and plan your design to fit the hardware - or just wing it and write down what you wanted, and hope for the best - in the latter scenario, the synthesis tool had to figure out how to fit your design best to the hardware, which even if you were mindful of how the chip worked, was still a hit and miss.
When you work in industry and either every cent counts, or you have to design for a fixed target, and somehow you're in the good graces of tooling, finding that changing a small thing suddenly makes your design 3x as big and half as fast is not acceptable.
HLS was this, but on steroids - you never knew what you were going to get, sometimes it worked well, sometimes not at all.
I'm sure tooling has evolved back then but I'd still guess spending the extra engineering effort is often well worth it when your chips cost five figures.
Yup, HLS is ridiculously fickle in that regard. In our lab we had the case that swapping out a C-style array T[] for a C++ std::array 10x-ed our resource consumption with no explanation.
And also the general problem of scribing resource use to the different components isn't easy, because thz way control flow is structured heavily alters that
Of course, that's what I'm trying to fix with SUS :p