IMO Intel should stick a "please query the size of the cache line if you care about it's length" clause into APX, to push code today to stop #defining CACHE_LINE_SIZE (64) on x86.
CPUID EAX=1, bits 8-15 (i.e., second byte) of EBX in the result tell you the cache line size. It's been there since Pentium 4, apparently.
You can also get line size for each cache level with CPUID EAX=4, along with the set-associativity and other low-level cache parameters.
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CPUID EAX=1, bits 8-15 (i.e., second byte) of EBX in the result tell you the cache line size. It's been there since Pentium 4, apparently.
You can also get line size for each cache level with CPUID EAX=4, along with the set-associativity and other low-level cache parameters.