TinyTapeout is cool, but the size of what you can do there is many orders of magnitude smaller than a Linux-capable OR1K core and surrounding SoC!
The typical project is more like a binary counter, or a BCD to 7-segment decoder.
I don't think you would even be able to fit a 6502 -- not the core, but also you can't have that many pins.
I think one was done with a bit-serial SeRV RV32I CPU (which is 125 LUT6 and 164 flip-flops when done in a Xilinx FPGA), but without the CPU registers fitting on the chip.
Yeah it really is for tiny chips. It is fabulous learning experience though, which is also the purpose of the project. Maybe in a few years we will have Smalltapeout where we can do microcontroller/microprocessor grade in the same way.
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TinyTapeout is cool, but the size of what you can do there is many orders of magnitude smaller than a Linux-capable OR1K core and surrounding SoC!
The typical project is more like a binary counter, or a BCD to 7-segment decoder.
I don't think you would even be able to fit a 6502 -- not the core, but also you can't have that many pins.
I think one was done with a bit-serial SeRV RV32I CPU (which is 125 LUT6 and 164 flip-flops when done in a Xilinx FPGA), but without the CPU registers fitting on the chip.
Yeah it really is for tiny chips. It is fabulous learning experience though, which is also the purpose of the project. Maybe in a few years we will have Smalltapeout where we can do microcontroller/microprocessor grade in the same way.