Optimistically tagging on here as it's a similar sort of question.
Say one lone developer gets a bit carried away with verilog and ends up with a description for a chip. I know there's an odd lot style of thing where you can get your chip drawn on a wafer along with a load of other chips from other people. There's probably a way of getting someone who knows what they're doing to attach wires to it, wrap it in plastic or whatever else is involved in "packaging".
Where does one get started with that, and what's the ballpark cost? I'm assuming a fair amount of the OP's $100k is SiFive labour, but I don't know how to guess whether a half dozen custom chips in some sort of packaging is of the order of 10s of dollars or 10s of thousands.
(edit: I've done a lot of software near hardware and have a vague idea that uploading the data to tsmc was called "tape out" and involved quite a lot of money, but I also vaguely remember talking to someone at a conference who had chips made as a hobby so there are some pieces missing from my mental model)
If you just want to put your verilog into an ASIC then it can be done fairly inexpensively these days.
For example:
https://efabless.com/chipignite
$10K for 100 packaged dies in QFN. Which is not totally out of hobby range (I've seen people spend way more on fixing up cars that have no business being fixed) and if you use their harness they'll solve most of the hard EE problems for you.
But you might consider why you're making the IC. If it's for the experience, sure. But if it's to make a commercial product, there's a lot more to it. For example, what's your IO solution...
Nice example, thank you. I have no interest in making a commercial product but some motivation to learn what lies below the ISA. Like you say, that's cheaper than some more common hobbies. I work in the software side of semiconductor companies so it's a reasonable spin on professional development too.
A friend recently discovered that PCBs can be ordered online for essentially zero cost and arrive in the mail and that surface mount soldering is an easy thing. Combined with a path for code to magic sand that's a whole world of dubious past times suddenly available.
Wait’ll you find out the same company that makes the PCBs will also source the parts and do the soldering for you, as well as 3D print the case — all in quantity 2 and up! All for incredibly cheap, and 6-day turnaround to your (west coast US) door. It’s a golden age for random hardware hacking. (Check out JLCPCB and PCBWay.)
You might find this course helpful then. There is a huge amount of information you need to consume to make an IC so having it all organized for you is pretty valuable. It will save you many, many, hours. :)
If you just want to learn how CPUs are designed then get an FPGA. The process of running a chip on an FPGA is very similar to the process of getting a custom ASIC built.
Thanks for mentioning e-fabless. When I saw $100k, the first thing I thought was "cool, now remove a zero". I love the capabilities the future is bringing.
The secret is that 180nm nodes are so legacy that they have a ton of spare cycles for educational and apparently now hobbyists. Lots of various businesses are offering services now that sell the ancient 180nm node.
Overall, the plan is much like OSHPark. You build a die that can be paired up with all of the other customers for a run. If say 300 wafers are made with 1000 different designs on it, everyone gets 300ish chips (before errors) and 1000 designers are happy.
*Made up numbers of course. I'm not in the business.
If say 300 wafers are made with 1000 different designs on it, everyone gets 300ish chips
That's not how it works. The same pattern, called a "reticule" [1] is duplicated 300 times over the wafer. One wafer gives you 300 copies of whatever set of dies fit into one reticule.
[1] it's to do with the size of the optical/UV lenses that are used in mask-making
That's true but they keep upping the capabilities of what the designer can do at 180nm. Based on the wait times for my jobs, there's not a lot of spare cycles, at least at the foundries I use.
Its more likely that 180nm fabs are idling so much that they've made the decision to close. There's only so low that the prices can go before these businesses don't think its worth staying in business anymore.
I've heard that over the long term, 28nm should theoretically be the "long term cost-efficient node". The 65nm and other nodes are all cheaper in practice because these factories are fully paid off by now.
It was something about 300mm wafers and overall tooling being shared with 28nm with the latest nodes + overall investments. While 200mm likely will be shutdown over the long term (but 200mm wafers will remain the cheapest solution in the short term).
So under these expectations, I'd say that 180nm, 65nm, and other old nodes will slowly shut down as everyone moves to the long-term most efficient node. Still, having the oldest nodes stay open for the educational / hobbyist / experimental R&D for some commerical companies makes sense. Especially since the wafers are smaller and thus overall runs can be smaller.
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Optimistically tagging on here as it's a similar sort of question.
Say one lone developer gets a bit carried away with verilog and ends up with a description for a chip. I know there's an odd lot style of thing where you can get your chip drawn on a wafer along with a load of other chips from other people. There's probably a way of getting someone who knows what they're doing to attach wires to it, wrap it in plastic or whatever else is involved in "packaging".
Where does one get started with that, and what's the ballpark cost? I'm assuming a fair amount of the OP's $100k is SiFive labour, but I don't know how to guess whether a half dozen custom chips in some sort of packaging is of the order of 10s of dollars or 10s of thousands.
(edit: I've done a lot of software near hardware and have a vague idea that uploading the data to tsmc was called "tape out" and involved quite a lot of money, but I also vaguely remember talking to someone at a conference who had chips made as a hobby so there are some pieces missing from my mental model)
If you just want to put your verilog into an ASIC then it can be done fairly inexpensively these days.
For example: https://efabless.com/chipignite $10K for 100 packaged dies in QFN. Which is not totally out of hobby range (I've seen people spend way more on fixing up cars that have no business being fixed) and if you use their harness they'll solve most of the hard EE problems for you.
But you might consider why you're making the IC. If it's for the experience, sure. But if it's to make a commercial product, there's a lot more to it. For example, what's your IO solution...
Nice example, thank you. I have no interest in making a commercial product but some motivation to learn what lies below the ISA. Like you say, that's cheaper than some more common hobbies. I work in the software side of semiconductor companies so it's a reasonable spin on professional development too.
A friend recently discovered that PCBs can be ordered online for essentially zero cost and arrive in the mail and that surface mount soldering is an easy thing. Combined with a path for code to magic sand that's a whole world of dubious past times suddenly available.
Wait’ll you find out the same company that makes the PCBs will also source the parts and do the soldering for you, as well as 3D print the case — all in quantity 2 and up! All for incredibly cheap, and 6-day turnaround to your (west coast US) door. It’s a golden age for random hardware hacking. (Check out JLCPCB and PCBWay.)
You might find this course helpful then. There is a huge amount of information you need to consume to make an IC so having it all organized for you is pretty valuable. It will save you many, many, hours. :)
https://zerotoasiccourse.com
If you just want to learn how CPUs are designed then get an FPGA. The process of running a chip on an FPGA is very similar to the process of getting a custom ASIC built.
Thanks for mentioning e-fabless. When I saw $100k, the first thing I thought was "cool, now remove a zero". I love the capabilities the future is bringing.
https://tinytapeout.com/
Cool concept!
The secret is that 180nm nodes are so legacy that they have a ton of spare cycles for educational and apparently now hobbyists. Lots of various businesses are offering services now that sell the ancient 180nm node.
Overall, the plan is much like OSHPark. You build a die that can be paired up with all of the other customers for a run. If say 300 wafers are made with 1000 different designs on it, everyone gets 300ish chips (before errors) and 1000 designers are happy.
*Made up numbers of course. I'm not in the business.
That's not how it works. The same pattern, called a "reticule" [1] is duplicated 300 times over the wafer. One wafer gives you 300 copies of whatever set of dies fit into one reticule.
[1] it's to do with the size of the optical/UV lenses that are used in mask-making
That's true but they keep upping the capabilities of what the designer can do at 180nm. Based on the wait times for my jobs, there's not a lot of spare cycles, at least at the foundries I use.
180nm is declining as far as I'm aware.
Its more likely that 180nm fabs are idling so much that they've made the decision to close. There's only so low that the prices can go before these businesses don't think its worth staying in business anymore.
I've heard that over the long term, 28nm should theoretically be the "long term cost-efficient node". The 65nm and other nodes are all cheaper in practice because these factories are fully paid off by now.
It was something about 300mm wafers and overall tooling being shared with 28nm with the latest nodes + overall investments. While 200mm likely will be shutdown over the long term (but 200mm wafers will remain the cheapest solution in the short term).
So under these expectations, I'd say that 180nm, 65nm, and other old nodes will slowly shut down as everyone moves to the long-term most efficient node. Still, having the oldest nodes stay open for the educational / hobbyist / experimental R&D for some commerical companies makes sense. Especially since the wafers are smaller and thus overall runs can be smaller.