Indirect addressing was evaluated for RISC-V, and found to not be worth the required added complexity and encoding space.
wtf?
If it was ever suggested by someone (and would NEVER be by Krste, Andrew, Yunsup, or Dave) then any evaluation would take less than 1 second before the "HELL NO!"
TWO instructions sizes, in the currently ratified ISA. And you can tell the size by looking at just 2 bits in the first byte of the instruction (the LSBs).
That is very far from "variable-length" in the sense of VAX or M68k or x86.
... was found to be highly beneficial to code density, and doable in a manner that does not add too much decode complexity
Commercially known in microprocessors since at least SuperH 2A and Arm Thumb2. Not to mention 3 lengths (2, 4 or 6 bytes) in IBM 360, also decodable from just 2 bits in the instruction. Also CDC 6600 (arguably the first RISC), Cray-1 (also recognizably RISC), the first version of IBM 801, and Berkeley RISC-II (obviously familar to the RISC-V designers).
And yes, RISC-V designers believe that addressing more complex than base+offset is a net loss in processor efficiency. You might need very slightly fewer instructions overall in a program, but it costs more transistors, silicon, and therefore dollars, and might even lower the achievable clock speed by more than the saved instructions.
Some companies implementing RISC-V don't quite believe that (e.g. Andes, THead) and add more complex addressing modes as custom extensions. Once they've spent the silicon then you might as well use it -- same with WCH's shadow registers or automatic push/pop for interrupt handling (depending on the core) -- but it's not proven it's actually the best use of additional silicon [1].
Let the market decide.
If complex addressing wins then RISC-V always has the possibility to add a standard extension. It's much harder to take unneeded features away.
[1] admittedly the equation is different with a single-core microcontroller in a package, vs a chip with large numbers of cores (whether all the same, or all RISC-V, or not). On a stand-alone microcontroller the die size is often determined by fitting the pads around the outside, and if you don't use all the silicon inside that then it's wasted.
Comments
wtf?
If it was ever suggested by someone (and would NEVER be by Krste, Andrew, Yunsup, or Dave) then any evaluation would take less than 1 second before the "HELL NO!"
TWO instructions sizes, in the currently ratified ISA. And you can tell the size by looking at just 2 bits in the first byte of the instruction (the LSBs).
That is very far from "variable-length" in the sense of VAX or M68k or x86.
Commercially known in microprocessors since at least SuperH 2A and Arm Thumb2. Not to mention 3 lengths (2, 4 or 6 bytes) in IBM 360, also decodable from just 2 bits in the instruction. Also CDC 6600 (arguably the first RISC), Cray-1 (also recognizably RISC), the first version of IBM 801, and Berkeley RISC-II (obviously familar to the RISC-V designers).
Had to re-read a few times until it hit me. I didn't mean indirect but complex addressing.
Ok, that makes more sense.
And yes, RISC-V designers believe that addressing more complex than base+offset is a net loss in processor efficiency. You might need very slightly fewer instructions overall in a program, but it costs more transistors, silicon, and therefore dollars, and might even lower the achievable clock speed by more than the saved instructions.
Some companies implementing RISC-V don't quite believe that (e.g. Andes, THead) and add more complex addressing modes as custom extensions. Once they've spent the silicon then you might as well use it -- same with WCH's shadow registers or automatic push/pop for interrupt handling (depending on the core) -- but it's not proven it's actually the best use of additional silicon [1].
Let the market decide.
If complex addressing wins then RISC-V always has the possibility to add a standard extension. It's much harder to take unneeded features away.
[1] admittedly the equation is different with a single-core microcontroller in a package, vs a chip with large numbers of cores (whether all the same, or all RISC-V, or not). On a stand-alone microcontroller the die size is often determined by fitting the pads around the outside, and if you don't use all the silicon inside that then it's wasted.