No way. Quite the opposite. ARM64 is quite similar to e.g. RISC-V in most respects other than the use of condition codes.
POWER has instructions like RLIMI, DOZ, and STHBRX on the "complex" side.
There is nothing complex or "un-RISC" about any of those.
RLIMI is similar to Arm32 BFI or Arm64 UBFM.
DOZ is just subtract with the output zeroed if the MSB is 1. It is easily implemented with just a handful of straight-line instructions in any ISA with min/max or slt or for that matter asr i.e. in hardware with a simple combinatorial add-on to standard subtraction.
STHBRX is just a little-endian store (on big-endian POWER). Plenty of other RISC ISAs (whether big-endian or little-endian) have that.
things like the "AAD" instruction did a lot of computing work in one bite
Less than other ISAs with a one-shot decimal add instruction (or mode e.g. 6502). Once again, it's a very simple combinatorial circuit -- no CISCy microcode or control flow needed.
There were also RISC register-memory machines at the time the distinction was meaningful.
Comments
No way. Quite the opposite. ARM64 is quite similar to e.g. RISC-V in most respects other than the use of condition codes.
There is nothing complex or "un-RISC" about any of those.
RLIMI is similar to Arm32 BFI or Arm64 UBFM.
DOZ is just subtract with the output zeroed if the MSB is 1. It is easily implemented with just a handful of straight-line instructions in any ISA with min/max or slt or for that matter asr i.e. in hardware with a simple combinatorial add-on to standard subtraction.
STHBRX is just a little-endian store (on big-endian POWER). Plenty of other RISC ISAs (whether big-endian or little-endian) have that.
Less than other ISAs with a one-shot decimal add instruction (or mode e.g. 6502). Once again, it's a very simple combinatorial circuit -- no CISCy microcode or control flow needed.
Name one.