Power is applied to the chip, and the RUN pin is high. The chip will be held in reset for as long as RUN is not high.
Is that a typo, or do I not understand this? Should it be "as long as RUN is high"? Because I assume that the RUN pin is active low, so as long as it is high, the chip will be held in reset?
Global asynchronous reset pin. Reset when driven low, run when driven high. If no external reset is required, this pin can be tied directly to IOVDD.
RST pins tend to be active-low, which is the same thing. Perhaps Raspberry Pi decided to call it the "run" pin instead of the "reset" one to avoid possibly confusing hobbyists?
Comments
Is that a typo, or do I not understand this? Should it be "as long as RUN is high"? Because I assume that the RUN pin is active low, so as long as it is high, the chip will be held in reset?
Nope. RUN is active-high:[0;pg12]
RST pins tend to be active-low, which is the same thing. Perhaps Raspberry Pi decided to call it the "run" pin instead of the "reset" one to avoid possibly confusing hobbyists?
[0]: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.p...
I think the second sentence should be in parentheses.