I suppose I shouldn't kick up dust here, because I left EDA programming...
But man, EDA programing is not one of those things you can just take a 6-week bootcamp and start hacking away on. Typically, you eat raman for 5-7 years to get a Ph.D., then you spend 5-10 years as a newb making your chops. And nobody takes you seriously until you've done the "cursus honorarium" of working for Synopsys, Cadence, and one or two chip companies.
Virtually every problem is NP-Complete, and the problem size is doubling every few years because of Moore's law. You need to learn circuit theory, computational geometry, optimization, transmission line theory---and you've got to keep up with all the cool programming techniques, like lock-free programming--because you are working on next-generation sized programs using this generation's computers.
What I'm trying to say is that its like a 20-year journey to be able to write this kind of software. And now, you've got to compete against....free?
I agree schools need access to these tools, but if we are going to make Chip Fabrication a national priority, we'll need to spend money not just on subsidies to billion-dollar companies, but we also need ensure that there is a solid pipeline of skilled and trained people to make the whole thing work.
Cut the schools a check big enough for them to buy the tools they need at a price which is commensurate with the expertise it takes to build them.
It's true that you require a very rare and profound skill set to develop those tools (i.e. experts in software as well as chip design) but it's not as complicated as you describe. Scaling is trivial when you've got your data architecture right (because chip designs and layouts scale like maps basically) and there are zillions of low hanging fruits to harvest because any halfway modern UI or tool flow will easily outperform the interface mess that the commercial tools are offering you. People who are using open source EDA tools for automated/ai-assisted chip designs are already demonstrating this in publications this btw. Moreover, there is more than advanced node VLSI. You have analog, custom digital, RF, cryo, etc., etc., where better automation, more flexibility in workflow and interfaces, and dramatically reduced costs for tool access could actually revolutionize the entire field on a very small time scale.
Comments
I suppose I shouldn't kick up dust here, because I left EDA programming...
But man, EDA programing is not one of those things you can just take a 6-week bootcamp and start hacking away on. Typically, you eat raman for 5-7 years to get a Ph.D., then you spend 5-10 years as a newb making your chops. And nobody takes you seriously until you've done the "cursus honorarium" of working for Synopsys, Cadence, and one or two chip companies.
Virtually every problem is NP-Complete, and the problem size is doubling every few years because of Moore's law. You need to learn circuit theory, computational geometry, optimization, transmission line theory---and you've got to keep up with all the cool programming techniques, like lock-free programming--because you are working on next-generation sized programs using this generation's computers.
What I'm trying to say is that its like a 20-year journey to be able to write this kind of software. And now, you've got to compete against....free?
I agree schools need access to these tools, but if we are going to make Chip Fabrication a national priority, we'll need to spend money not just on subsidies to billion-dollar companies, but we also need ensure that there is a solid pipeline of skilled and trained people to make the whole thing work.
Cut the schools a check big enough for them to buy the tools they need at a price which is commensurate with the expertise it takes to build them.
It's true that you require a very rare and profound skill set to develop those tools (i.e. experts in software as well as chip design) but it's not as complicated as you describe. Scaling is trivial when you've got your data architecture right (because chip designs and layouts scale like maps basically) and there are zillions of low hanging fruits to harvest because any halfway modern UI or tool flow will easily outperform the interface mess that the commercial tools are offering you. People who are using open source EDA tools for automated/ai-assisted chip designs are already demonstrating this in publications this btw. Moreover, there is more than advanced node VLSI. You have analog, custom digital, RF, cryo, etc., etc., where better automation, more flexibility in workflow and interfaces, and dramatically reduced costs for tool access could actually revolutionize the entire field on a very small time scale.
You are obviously not a golfer....