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Comment on Launch HN: SiLogy (YC W24) – Chip design and verification in the cloudparent

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The functionality on offer here is equivalent to about 30 lines of Github Actions YAML to install verilator, run the tests, and upload the coverage information. [1]

Generating waveforms is free, Verilator already does that if you pass it the appropriate argument, either --trace or --trace-fst. We usually control that with a single CMake option.

Complex workflows can get nutty, but what's illustrated here is not a complex workflow.

[1]: https://github.com/NYU-Processor-Design/component-template/b...

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