I haven't been thinking about an FPGA myself. Mostly because I don't know verilog/vhdl well enough.
I've been thinking of how hard would it be to take two 32k SRAMs and an AVR and do some fancy bank switching to handle it. I know I could probably manage it by using the onchip support directly but then I'd end up with some memory inaccessible from addressing holes.
It seems like it should be possible to do, and then it would be easy to allow real IO and everything later when that's standardized.
Comments
I haven't been thinking about an FPGA myself. Mostly because I don't know verilog/vhdl well enough.
I've been thinking of how hard would it be to take two 32k SRAMs and an AVR and do some fancy bank switching to handle it. I know I could probably manage it by using the onchip support directly but then I'd end up with some memory inaccessible from addressing holes.
It seems like it should be possible to do, and then it would be easy to allow real IO and everything later when that's standardized.