Ugly thought - if "almost all" accesses are Read-Write consistent, maybe an exception list of addresses could be used?
Basically do the 4byte cell approach, and make most of your RAM the "fast" endianness, with some 4byte cells "correct" endianness, because you know they are being accessed in a way that cares. (Since you're interpreting, I'm guessing this is reasonably-easily detectable?)
It does put a "if-addr-on-exception-list" on your mem access path, but if that's a hash lookup it could be OK. If you can further guarantee that your text segments are always fast-endian, then your opcode dispatch loop can still go direct and miss out that test.
That would actually work, I guess :). I'm pretty sure the memcpy, memmove, etc. implementations I've seen for this architecture all work by copying one byte at a time (argh!) though, but that problem can be solved with some smart-if-ugly hackery.
But, as you said yourself, it would be kind of messy, in that it would be hard to be certain if it works in 100% of the cases.
I think it would be easier to just change the toolchain code and make it think the processor is little endian.
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Ugly thought - if "almost all" accesses are Read-Write consistent, maybe an exception list of addresses could be used?
Basically do the 4byte cell approach, and make most of your RAM the "fast" endianness, with some 4byte cells "correct" endianness, because you know they are being accessed in a way that cares. (Since you're interpreting, I'm guessing this is reasonably-easily detectable?)
It does put a "if-addr-on-exception-list" on your mem access path, but if that's a hash lookup it could be OK. If you can further guarantee that your text segments are always fast-endian, then your opcode dispatch loop can still go direct and miss out that test.
That would actually work, I guess :). I'm pretty sure the memcpy, memmove, etc. implementations I've seen for this architecture all work by copying one byte at a time (argh!) though, but that problem can be solved with some smart-if-ugly hackery.
But, as you said yourself, it would be kind of messy, in that it would be hard to be certain if it works in 100% of the cases.
I think it would be easier to just change the toolchain code and make it think the processor is little endian.