The cycle accurate assembly language has enabled a number of timing sensitive FIFO data processes. What had to be done with FPGA's before has some limited support with PIO. I hope RPI increases the number of instructions and simultaneous running PIO machines in the future.
It's great to have the PIO in a smaller/cheaper device, but if that is the kind of thing that you really like, I do want to mention the BeagleBone SPUs and the Parallax Propeller / Propeller2 are similar/more powerful implementations of this concept.
I've done similar things (for a Playstation 1/2 controller) bit-banging with 8-bit microcontrollers. They often include instruction timing information in the datasheets.
Comments
Looks like it was made possible by the Pico's PIO assembly/chip https://github.com/mackieks/MaplePad/blob/main/src/maple.pio
The cycle accurate assembly language has enabled a number of timing sensitive FIFO data processes. What had to be done with FPGA's before has some limited support with PIO. I hope RPI increases the number of instructions and simultaneous running PIO machines in the future.
It's great to have the PIO in a smaller/cheaper device, but if that is the kind of thing that you really like, I do want to mention the BeagleBone SPUs and the Parallax Propeller / Propeller2 are similar/more powerful implementations of this concept.
RE: Propeller2- at $10+/chip, I'm just going with an XC7A35T or the TI AM243X (actually less $ and substantially more RAM) or AM62X series CPUs.
33000 LUTs and 90 DSP48s are more than enough to do 10+ RISC-V cores, I don't understand the niche this product fills.
I've done similar things (for a Playstation 1/2 controller) bit-banging with 8-bit microcontrollers. They often include instruction timing information in the datasheets.
A PIO LUT instruction with a 256 entry deep, 32bits wide lookup table would absolutely make my day.