> "chip stacking obviously works in synergy with Intel’s 3D FinFETs — though curiously there is no sign of TSV on Intel’s roadmap"
Wouldn't chip stacking exacerbate heat dissipation issues? It seems to me that desktop chips would stand to gain far less from this approach, so why should it be surprising that Intel isn't rushing into it?
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> "chip stacking obviously works in synergy with Intel’s 3D FinFETs — though curiously there is no sign of TSV on Intel’s roadmap"
Wouldn't chip stacking exacerbate heat dissipation issues? It seems to me that desktop chips would stand to gain far less from this approach, so why should it be surprising that Intel isn't rushing into it?
But what about servers ? memory bandwidth is the biggest problem facing servers, and stacking solves it nicely.
And when you put chips side by side like xilinx's new chip, the heating issue is solvable.
You would reduce mean distance between all components and, depending on the graph of connections, save a lot on resistance losses.
I wonder if you could etch channels for liquid coolant directly into every 3rd layer or so...
http://www.eetimes.com/electronics-news/4077160/IBM-GIT-demo...