Skip to content

Comment on SimulaVR FPGA Image Processing Pipelineparent

Comments

SLVS-EC has some very minor issues when interfacing (DC offset compliance) which requires a hack in detecting when the link is up. And yeah, MIPI D-PHY is a royal pain unless you have native support (Xilinx, Lattice, Intel Agilex 5). C-PHY even more so.

C-PHY is so incredibly fucked up.

AboutSource Built by g1lg1l

Hackerly is an independent reader for Hacker News, built on the public HN API. Not affiliated with Y Combinator.