- Ascenium: Software-defined CPU without an instruction set. Highly parallel architecture with extensive compiler integration.
This is marketing BS if I've ever heard it. Their "instruction set" is LLVM. They're doing nothing more than what Transmeta (dynamic/programmable ISA) or Lisp/Arm-Java machines (running higher level code at a machine level) did before them.
Yeah, agree on the instruction set part - however they are moving the abstraction level to a point where there should be more room for optimization. I don't know enough about the technology to make any judgement - I just know a really smart guy who works there. Hopefully it turns into something cool :-)
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This is marketing BS if I've ever heard it. Their "instruction set" is LLVM. They're doing nothing more than what Transmeta (dynamic/programmable ISA) or Lisp/Arm-Java machines (running higher level code at a machine level) did before them.
Yeah, agree on the instruction set part - however they are moving the abstraction level to a point where there should be more room for optimization. I don't know enough about the technology to make any judgement - I just know a really smart guy who works there. Hopefully it turns into something cool :-)