As the number of cores per socket is steadily increasing it is becoming more difficult to keep all of the cores on a single computer operating efficiently. A higher clock rate per core, or more cores per socket, is not very useful if they are all waiting on memory.
Now imagine a large amount of memory connected to the cores through tiny metal wires on the chip itself. Now imagine that it's split into a bunch of small independent memories with enormous bandwidth, with data automatically migrating between them to cut down on wire delays. Give it a few years, and this could be reality.
Comments
This would be a huge boon for scientific computing. The data is often huge, but all of it must be constantly pushed through the CPU every iteration.
As the number of cores per socket is steadily increasing it is becoming more difficult to keep all of the cores on a single computer operating efficiently. A higher clock rate per core, or more cores per socket, is not very useful if they are all waiting on memory.
Now imagine a large amount of memory connected to the cores through tiny metal wires on the chip itself. Now imagine that it's split into a bunch of small independent memories with enormous bandwidth, with data automatically migrating between them to cut down on wire delays. Give it a few years, and this could be reality.
Unless we are considering coupling lots of memory to the cores themselves, bypassing slow external buses.