Comment on RISC-V J extension – Instructions for JITsparentComments−my1234yStrictly 4 bits. For the Morello prototype architecture with full CHERI, it’s 1 bit for each 16 bytes region. (capability valid bit)−saagarjha4yOf course, CHERI faces very different challenges than MTE does ;)
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Strictly 4 bits. For the Morello prototype architecture with full CHERI, it’s 1 bit for each 16 bytes region. (capability valid bit)
Of course, CHERI faces very different challenges than MTE does ;)