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Comment on Being fair about memory safety and performanceparent

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Speculative execution enables continuing along the predicted branch without stopping. You do need to have the ~2 instructions to get the length test input on hand but that usually can be eaten by insn level parallelism without hurting the latency of the array operation.

Do you have any evidence of this claim? Perhaps a benchmark?

This doesn't align with any of my performance optimization experience.

I went looking, and seems I have to walk my claim back somewhat. Wide issue OoO processors hide a lot of the overhead but not all of it.

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