Given that I2C and SPI are addressable replacing them with a bare TTL serial interface would be horrendous because now everyone needs to invent their own addressing scheme which they already had with the other two.
I guess with RxTx or UART as some seem to call it, you only have one device per RxTx pair so you need more IO pins... true didn't think of that, but my only real uses are 1) make some modem like thing for my C64 and 2) talk to a LoRa radio from my Raspberry Zero in both those cases I'm actually ok with having only one pheriperal and there is nothing else I want except the connection, all other things use other protocols.
In my experience has been that there exist essentially 2 types of SPI, one addressable by CS, the other (more i2c-like) by the first byte (CS still required to frame the transactions.
I'm working with one of the latter type at the moment that's even worse, it daisy chains chips with each editing the address as it passes through until it hits one where it's 0, they share a CS and a wired-or interrupt, but avoid the need to have 32 CS pins
I’ve never seen SPI that doesn’t require a CS line. The whole way that daisy chaining works is this. Do you have a device off hand that uses addressable SPI, I want to see how they explain it in a datasheet.
I'm afraid the two I can think of have non-publicly available data sheets: one is a cablecrypto device, the other a SLIC. The SLIC is the one with the daisy chain - they want to be able to build phone systems with a SLIC for every slot in a T1 frame - so 24 SLICs - they're trying to avoid 24 CS pins and 24 interrupts on the attached signalling CPU
Chip selects are optional. You can daily chain multiple spi devices and push the data out in a contiguous block. All the chip selects are tied together and only one cs line is used from the cpu.
For some simple SPI devices, sometimes. Many SPI devices, especially more complex ones, won't let you shift data through the device without attempting to interpret it.
Or will shift out something completely different, like the response to the last command they received, just FFs so you can three wire in the general case, or even just garbage.
No, I don't, but at the point where you're integrating a UART, adding a couple of logic gates on the data input doesn't seem too much of a stretch.
I'm not saying using UARTs instead of SPI is a good idea! I'm just saying the reason that it's not a good idea is not because UART's don't have /SS inputs.
But then how is the device supposed to know when it can respond? Most uart devices don't respect flow control. They assume they can transmit at any point.
Comments
Given that I2C and SPI are addressable replacing them with a bare TTL serial interface would be horrendous because now everyone needs to invent their own addressing scheme which they already had with the other two.
0/10 suggestion
I guess with RxTx or UART as some seem to call it, you only have one device per RxTx pair so you need more IO pins... true didn't think of that, but my only real uses are 1) make some modem like thing for my C64 and 2) talk to a LoRa radio from my Raspberry Zero in both those cases I'm actually ok with having only one pheriperal and there is nothing else I want except the connection, all other things use other protocols.
SPI isn't addressable.
In my experience has been that there exist essentially 2 types of SPI, one addressable by CS, the other (more i2c-like) by the first byte (CS still required to frame the transactions.
I'm working with one of the latter type at the moment that's even worse, it daisy chains chips with each editing the address as it passes through until it hits one where it's 0, they share a CS and a wired-or interrupt, but avoid the need to have 32 CS pins
I’ve never seen SPI that doesn’t require a CS line. The whole way that daisy chaining works is this. Do you have a device off hand that uses addressable SPI, I want to see how they explain it in a datasheet.
I'm afraid the two I can think of have non-publicly available data sheets: one is a cablecrypto device, the other a SLIC. The SLIC is the one with the daisy chain - they want to be able to build phone systems with a SLIC for every slot in a T1 frame - so 24 SLICs - they're trying to avoid 24 CS pins and 24 interrupts on the attached signalling CPU
There are some Microchip chips that implement weird SPI/I2C hybrid which does I2C-like slave addressing over SPI. But thats it for the addressing.
Yes it is - that's what /SS is for.
Chip selects are optional. You can daily chain multiple spi devices and push the data out in a contiguous block. All the chip selects are tied together and only one cs line is used from the cpu.
For some simple SPI devices, sometimes. Many SPI devices, especially more complex ones, won't let you shift data through the device without attempting to interpret it.
Or will shift out something completely different, like the response to the last command they received, just FFs so you can three wire in the general case, or even just garbage.
Flash memory devices use the CS line as an integral part of the protocol. It is definitely not optional.
If that counts then you can do exactly the same thing with a UART-based protocol, no?
Do you know of any uart hardware that'll only latch on /SS active?
No, I don't, but at the point where you're integrating a UART, adding a couple of logic gates on the data input doesn't seem too much of a stretch.
I'm not saying using UARTs instead of SPI is a good idea! I'm just saying the reason that it's not a good idea is not because UART's don't have /SS inputs.
But then how is the device supposed to know when it can respond? Most uart devices don't respect flow control. They assume they can transmit at any point.
Fair point.