Barrel processors still need to be programmed with parallelism and cache behavior in mind. And if normal imperative code can't be reused with minimal modification, than such a device holds little appeal over GPUs (as Intel found out with Xeon Phi).
"There are quirks to designing software for these systems, but they don’t involve safety."
Parallel programming is intrinsically racey. Even if hardware could enforce safety like you're saying (which it can't, even in a single thread) it would imply a sequentially consistent memory model, i.e. the antithesis of any parallel machine.
Comments
Barrel processors still need to be programmed with parallelism and cache behavior in mind. And if normal imperative code can't be reused with minimal modification, than such a device holds little appeal over GPUs (as Intel found out with Xeon Phi).
"There are quirks to designing software for these systems, but they don’t involve safety."
Parallel programming is intrinsically racey. Even if hardware could enforce safety like you're saying (which it can't, even in a single thread) it would imply a sequentially consistent memory model, i.e. the antithesis of any parallel machine.