In the field of high performance processor microarchitecture, one goal is to increase performance by executing a maximum number of instructions in parallel (increase IPC). For this purpose we identify dependencies between instructions. We identify 4 types of dependencies between instruction registers: Read after Write (RaW), Read after Read (RaR), Write after Read (WaR) and Write after Write (WaW). (the same kind of dependencies exist with memory)

Among these dependencies some are caused by the reduced number of registers, with more registers they can be removed, this is called false dependencies. 3 of these 4 dependencies are false dependencies: RaR, WaR, WaW. And with register renaming techniques we can eliminate these dependencies and therefore increase IPC.

Only the Read after Write (RaW) dependency remains and it really determines what can be executed in parallel or not in modern machines. The whole point of value speculation is to break the RaW dependency to increase IPC.

The papers you quoted cover value speculation in hardware, while the article covers value speculation in software.

The possibilities and gains relative to these 2 approaches differ since: in software we can predict a whole expression, while in hardware we can only predict a static value (or a pattern of values). But in hardware it doesn't require any particular effort at compile time and it doesn't increase the code size.

I recently spoke with one of the researchers you mentioned (who deals with value speculation in hardware) and he acknowledged that the performance gain is currently quite low relative to the amount of hardware to be added.

But maybe the research in hardware value speculation will lead to a higher performance gain? Maybe in software there are more realistic gains? Maybe even a mix of hardware and software can make the value speculation powerful?

Imagine an instruction `predict <rd>, <r1>, <r2>` where rd takes the value of r1 but the processor is allowed to use the value of r2 as a value prediction