Yes, most implementations of x86 translate opcodes into equivalent RISC-like micro-ops.
But this was necessary to achieve any kind of real performance with x86. It's a terribly-designed architecture where all of the instructions are scattered all over the map. There's no unifying design, and most operations that should be simple to implement require scads of silicon. Much of the power wasted on x86 chips is in that instruction decode hardware. It's terribly inefficient. (It's also a horrible instruction set to deal with.)
Comments
Yes, most implementations of x86 translate opcodes into equivalent RISC-like micro-ops.
But this was necessary to achieve any kind of real performance with x86. It's a terribly-designed architecture where all of the instructions are scattered all over the map. There's no unifying design, and most operations that should be simple to implement require scads of silicon. Much of the power wasted on x86 chips is in that instruction decode hardware. It's terribly inefficient. (It's also a horrible instruction set to deal with.)